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AT88SC6416C
Figure 2.
Block Diagram
V CC
GND
SCL/CLK
SDA/IO
RST
Power
Management
Synchronous
Interface
Asynchronous
ISO Interface
Reset Block
Authentication,
Encryption and
Certification Unit
Data Transfer
Password
Verification
Answer to Reset
Random
Generator
EEPROM
2.
2.1.
2.2.
2.3.
2.4.
Pin Descriptions
Supply Voltage (V CC )
The V CC input is a 2.7V to 5.5V positive voltage supplied by the host.
Clock (SCL/CLK)
In the asynchronous T = 0 protocol, the SCL/CLK input is used to provide the device with a carrier frequency f . The
nominal length of one bit emitted on I/O is defined as an “elementary time unit” (ETU) and is equal to 372/ f . When the
synchronous protocol is used, the SCL/CLK input is used to positive edge clock data into the device and negative edge
clock data out of the device.
Reset (RST)
The AT88SC6416C provides an ISO 7816-3 compliant asynchronous answer to reset sequence. When the reset
sequence is activated, the device will output the data programmed into the 64-bit answer-to-reset register. An internal
pull-up on the RST input pad allows the device to be used in synchronous mode without bonding RST. The
AT88SC6416C does not support the synchronous answer-to-reset sequence.
Serial Data (SDA/IO)
The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wired with any number of
other open drain or open collector devices. An external pull-up resistor should be connected between SDA and VCC.
The value of this resistor and the system capacitance loading the SDA bus will determine the rise time of SDA. This
rise time will determine the maximum frequency during read operations. Low value pull-up resistors will allow higher
frequency operations while drawing higher average power. SDA/IO information applies to both asynchronous and
synchronous protocols.
When the synchronous protocol is used, the SCL/CLK input is used to positive edge clock data into the device and
negative edge clock data out of the device.
3
5015KS–SMEM–08/09
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